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Synthetic Elements for Moving Line Arrays

Award Information
Agency: Department of Defense
Branch: Navy
Contract: N65538-10-M-0097
Agency Tracking Number: N093-204-0128
Amount: $99,929.00
Phase: Phase I
Program: SBIR
Solicitation Topic Code: N093-204
Solicitation Number: 2009.3
Timeline
Solicitation Year: 2009
Award Year: 2010
Award Start Date (Proposal Award Date): 2010-04-15
Award End Date (Contract End Date): 2010-10-25
Small Business Information
5885 Trinity Parkway Suite 230
Centreville, VA 20120
United States
DUNS: 135121148
HUBZone Owned: No
Woman Owned: No
Socially and Economically Disadvantaged: No
Principal Investigator
 Walt Allensworth
 Vice President
 (301) 840-9722
 wallensworth@adaptivemethods.com
Business Contact
 Judy Barhorst
Title: Director of Contracts
Phone: (703) 968-8040
Email: jbarhorst@adaptivemethods.com
Research Institution
N/A
Abstract

Uniformly spaced line arrays (ULAs) exhibit spatial ambiguities governed by to the Nyquist sampling theorem. This results in grating-lobes which degrade array gain and also results in direction of arrival estimation ambiguities for signals of interest. The challenge associated with the formation of synthetic elements for line arrays (SELA) to eliminate grating lobes and perform failed channel recovery for ULAs is discussed. Objectives of the solicitation and the Phase I Basic and Option work are given. These objectives are to develop methodologies and SELA algorithms for exploiting towed array motion to process higher frequency regions at all steered directions in order to use the full frequency capability of a ULA; and to develop methods to mitigate the effects of missing array elements to improve beamformer performance in a degraded submarine (or other) towed array. A schedule and work plan is presented that is focused around the development and evaluation of algorithms addressing these two objectives. A Phase I Option work plan is submitted in which we propose developing a framework for real-time SELA algorithm implementation, performing an analysis of alternatives that includes estimate processor timing and sizing estimates for the proposed algorithms.

* Information listed above is at the time of submission. *

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