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Extremelly High Bandwidth Rad Hard Data Acquisition System

Award Information
Agency: National Aeronautics and Space Administration
Branch: N/A
Contract: NNX09RA17C
Agency Tracking Number: 066680
Amount: $599,924.00
Phase: Phase II
Program: SBIR
Solicitation Topic Code: S4.01
Solicitation Number: N/A
Timeline
Solicitation Year: 2006
Award Year: 2009
Award Start Date (Proposal Award Date): 2009-09-30
Award End Date (Contract End Date): 2011-03-31
Small Business Information
27 Via Porto Grande
Rancho Palos Verdes, CA 90275-2049
United States
DUNS: 114422095
HUBZone Owned: No
Woman Owned: No
Socially and Economically Disadvantaged: No
Principal Investigator
 Sean Woyciehowsky
 Principal Investigator
 (310) 377-6029
 woycieho@adsantec.net
Business Contact
 Vladimir Katzman
Title: Business Official
Phone: (310) 377-6029
Email: traffic405@cox.net
Research Institution
N/A
Abstract

Analog-to-digital converters (ADCs) are the key components for digitizing high-speed analog data in modern data acquisition systems, which is a critical part of sensor/detector array readout electronics widely used by NASA. Unfortunately, commercially available ADCs consume high power and feature high system latency and poor linearity; especially at input bandwidths larger than 1GHz. In addition, these ADCs are not radiation tolerant due to the utilized process technologies and thus are susceptible to harmful total ionization dose and single event upset effects. Thus, they do not satisfy NASA's low-power, radiation tolerant, and high bandwidth (>20GHz) requirements. In response to the described needs, we propose to develop a monolithic high input bandwidth, radiation tolerant analog-to-digital converter (HIBRA), which will be implemented into a sealed metal-ceramic microwave package with an FPGA-friendly parallel interface and will feature an improved radiation tolerance, high sampling rate, extremely high input bandwidth, and advanced functionality. The ADC will utilize ADSANTEC's high-speed current-mode logic library of Total Ionization Dose-tolerant-by-technology and proprietary architectural cells. The fully functional ASIC will be fabricated in IBM SiGe technology at the end of Phase II.

* Information listed above is at the time of submission. *

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