Scalable Parallel Algorithms for Formal Verification of Software
We will develop a prototype of a GPU-based parallel Binary Decision Diagram (BDD) software package. BDDs are a data structure that satisfies some simple restrictions, resulting in a unique representation of a Boolean function regardless of its actual implementation. This property of BDDs allows the efficient solution of many problems. The proposed tool will exploit multi-core CPUs and the thousands of stream cores in the latest graphics processors (GPUs) , which were made accessible to programmers through specialized software development kits. These large numbers of stream cores in GPUs, and the possibility to execute non-graphics computations on them, open unprecedented levels of parallelism at a very low cost. In the last 8 years, GPUs had an increasing performance advantage of an order of magnitude relative to x86 CPUs. Furthermore, this performance advantage will continue to increase in the next 20 years because of the scalability of the chip manufacturing processes. The technical objectives will be to efficiently exploit the GPU parallelism in order to accelerate the execution of a BDD package, and to explore hybrid approaches that will combine this GPU-based BDD package with our GPU-based parallel SAT solver that we are currently developing in a NASA SBIR Phase II project. The goal will be to achieve increased speed, as well as scalability for much larger state spaces when formally verifying complex software for space applications. We anticipate increase in both speed and scalability by 1?2 orders of magnitude by the end of Phase I, and 3?4 orders of magnitude by the end of Phase II, compared to the current approaches.
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Aries Design Automation, LLC
2705 West Byron Street Chicago, IL 60618-3745
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