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Efficient Real-time Resource Allocation (ERRA) Co-processor

Award Information
Agency: Department of Defense
Branch: Air Force
Contract: FA8750-11-C-0087
Agency Tracking Number: O102-IA2-1072
Amount: $100,000.00
Phase: Phase I
Program: SBIR
Solicitation Topic Code: OSD10-IA2
Solicitation Number: 2010.2
Timeline
Solicitation Year: 2010
Award Year: 2011
Award Start Date (Proposal Award Date): 2010-12-01
Award End Date (Contract End Date): N/A
Small Business Information
15400 Calhoun Drive Suite 400
Rockville, MD -
United States
DUNS: 161911532
HUBZone Owned: No
Woman Owned: Yes
Socially and Economically Disadvantaged: No
Principal Investigator
 Sendil Rangaswamy
 Senior Scientist
 (301) 294-4756
 sendilr@i-a-i.com
Business Contact
 Mark James
Title: Director, Contracts and Proposals
Phone: (301) 294-5221
Email: mjames@i-a-i.com
Research Institution
 Stub
Abstract

Intelligent Automation, Inc. (IAI), with its partner University of Central Florida (UCF), propose to design, develop, and test an Efficient Real-time Resource Allocation (ERRA) co-processor. The optimized efficient resource allocation by ERRA co-processors is critical in decision-making process in mini-mobile platforms as events unfold in the field. This allows for intelligent decisions in the field during events even if the devices are overloaded with data bursts. The key innovations in the novel ERRA co-processor are: (1) high performance innovative co-processor architecture for simplex optimization, change point detection, and adaptive filtering that uses very less power to identify potentially important data, (2) optimal execution to achieve requisite performance with minimal power consumption that is critical for mobile platforms by efficient binding and freeing up of resources, (3) out-of-band secure execution of critical algorithms for collective processing in burst conditions, (4) innovative distributed processing: if the data identified to be processed is important and if the main processor is overloaded the next important data is processed in a neighbor processor after preempting its process, (5) optimized run time speedup in shared, distributed and hybrid memory conditions, and (6) scale up functionality for current and future mini mobile platforms architectures.

* Information listed above is at the time of submission. *

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