System Configuration Verification

In this Phase I SBIR project, The Athena Group, Inc. will develop an improved joint test action group (JTAG) implementation that incorporates support for autonomous board configuration verification, tamper detection and response, and the use of information assurance (IA) techniques to provide user authentication and confidentiality capabilities for JTAG diagnostics and maintenance functions. This improved JTAG implementation will preserve the considerable infrastructure investment in the electrical interface and low-level operating protocol of IEEE 1149.1 JTAG, and be fully compatible with existing devices that incorporate JTAG functionality. By leveraging the existing ubiquitous JTAG infrastructure, this technology may be employed immediately in new designs and can be easily retrofitted into current designs. Athena"s solution, called POST-JTAG, will combine Athena"s secure system-on-a-chip (SoC) technology with a JTAG test access port controller implementation to enable the desired capabilities. As a leading provider of semiconductor intellectual property, Athena is uniquely positioned and qualified to develop this technology and address the broad commercial and DoD markets for secure JTAG.