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RUSH: A Rad-Hard Unified Scalable Heterogeneous Processing Architecture

Award Information
Agency: National Aeronautics and Space Administration
Branch: N/A
Contract: NNX11CF46P
Agency Tracking Number: 104957
Amount: $99,992.00
Phase: Phase I
Program: SBIR
Solicitation Topic Code: S3.01
Solicitation Number: N/A
Timeline
Solicitation Year: 2010
Award Year: 2011
Award Start Date (Proposal Award Date): 2011-02-18
Award End Date (Contract End Date): 2011-09-29
Small Business Information
NJ
Fort Lee, NJ 07024-9212
United States
DUNS: 145051095
HUBZone Owned: No
Woman Owned: No
Socially and Economically Disadvantaged: No
Principal Investigator
 Brandon Beresini
 Principal Investigator
 (858) 605-6337
 beresini@gmail.com
Business Contact
 Houman Ghajari
Title: Business Official
Phone: (858) 272-8800
Email: houman@maxentric.com
Research Institution
 Stub
Abstract

Space presents a challenging environment for computing. Extendeddevelopment times and radiation tolerance requirements leave hardwareperformance a decade or more behind the terrestrial state-of-the-artat the time of deployment. Additionally, once deployed, hardwarechanges are impractical, encouraging a trend towards increasedsoftware programmability. However, topside pressure from applicationadvancements are forcing space-based platforms to improve throughputand latency while reducing power consumption. A popular approach toaddressing the tension between these requirements is the heterogeneousprocessing architecture. By providing multiple hardware tools thatoptimally support a subset of the anticipated workload, aheterogeneous architecture can offer a diverse processing toolset tothe application developer. However, programming these systems isextremely challenging because of variations in toolsets and datasharing interfaces. As a result, data sharing and dynamic workloadscheduling across heterogeneous architectures is often suboptimal andhindered by poor scalability. Maxentric proposes to solve this problemwith RUSH, a heterogeneous processing architecture with a unifiedprogramming model for rapid development. RUSH employs a rad-hardmulticore processor as a host and an FPGA as an accelerator chip. TheRUSH software layer unifies these architectures through an innovativeprogramming model described in the proposal.

* Information listed above is at the time of submission. *

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