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Software Defined Common Processing System (SDCPS)

Award Information
Agency: National Aeronautics and Space Administration
Branch: N/A
Contract: NNX09CB47C
Agency Tracking Number: 075268
Amount: $599,988.00
Phase: Phase II
Program: SBIR
Solicitation Topic Code: O1.05
Solicitation Number: N/A
Timeline
Solicitation Year: 2007
Award Year: 2009
Award Start Date (Proposal Award Date): 2009-09-22
Award End Date (Contract End Date): 2011-09-21
Small Business Information
1120 S. Capital of Texas Hwy, Bldg. 3, Suite 310
Austin, TX 78746-6460
United States
DUNS: 118514855
HUBZone Owned: No
Woman Owned: No
Socially and Economically Disadvantaged: No
Principal Investigator
 Kevin Shelby
 Principal Investigator
 (512) 382-8953
 shelby@coherentlogix.com
Business Contact
 Donald Gorsuch
Title: Business Official
Phone: (512) 382-8951
Email: gorsuch@coherentlogix.com
Research Institution
N/A
Abstract

Coherent Logix, Incorporated (CLX) proposes the development of a Software Defined Common Processing System (SDCPS) that leverages the inherent advantages of an integrated parallel processing architecture. Targeting a specific waveform (TBD) specified by NASA-GRC in terms of a high level functional model, e.g. Simulink, the study aims to examine system performance in a reference implementation based on the HADS2 development system configured for this purpose to include the HyperX signal processor, data converters and General Purpose Processor (GPP). Waveform implementation will be executed in stages: (i) port an implementation to the signal processing complex consisting of a single path per functional block (consuming multiple resources depending on the complexity of each block) (ii) extend the design to account for N-modular path redundancy aimed at enhancing system reliability (iii) integrate in the reference platform to enable real-time performance assessment, e.g. resource utilization, throughput efficiency and emulated radiation tolerance.

This effort is supported by extensive development underway at CLX to deliver a line of extremely high-performance per watt, runtime configurable signal processors. Based on a multi-core architecture, the intended processing system will enable model based waveform development applicable across a range of fault tolerant mission classes without sacrificing real-time throughput performance.

* Information listed above is at the time of submission. *

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