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Development of High-Definition (HD), Low-Light-Level Detector

Award Information
Agency: Department of Defense
Branch: Air Force
Contract: FA8650-08-M-5405
Agency Tracking Number: F073-043-0721
Amount: $100,000.00
Phase: Phase I
Program: SBIR
Solicitation Topic Code: AF073-043
Solicitation Number: 2007.3
Timeline
Solicitation Year: 2007
Award Year: 2008
Award Start Date (Proposal Award Date): 2008-01-07
Award End Date (Contract End Date): 2009-01-07
Small Business Information
12725 SW Millikan Way Suite 230
Beaverton, OR 97005
United States
DUNS: 124348652
HUBZone Owned: No
Woman Owned: No
Socially and Economically Disadvantaged: No
Principal Investigator
 George Williams
 President
 (971) 223-5646
 georgew@voxtel-inc.com
Business Contact
 George Williams
Title: President
Phone: (971) 223-5646
Email: georgew@voxtel-inc.com
Research Institution
N/A
Abstract

In this Phase I SBIR program, a low noise SOI CMOS high-definition (HD) low light level television (LLLTV) image sensor will be developed. The detector will be back-illuminated with a 300-micron thick silicon absorption region, for increased sensitivity and spectral-overlap with the night sky radiance. The imager will be configured with 1280 x 1024, 6-micron-square pixels, will operate at 60 frames per second, and will include a 14-bit analog-to-digital converter. The HD LLLTV Imager is based on a SOI (silicon-on-insulator) CMOS image sensor architecture. Fabricating imagers on SOI greatly improves performance. For example, CMOS circuitry is isolated from photo regions, allowing high-resistivity silicon to be employed. In addition, CMOS circuit ground returns for SOI are isolated, eliminating substrate bounce and transient coupling problems. This allows higher operating speeds and lower noise. SOI’s planar architecture also makes it easier to passivate surfaces for low dark-current generation. This advantage, in turn, makes the device much more resistant to high-energy radiation environments. Lower fixed pattern noise (FPN) and lower power consumption are also achieved. In Phase I, the HD image sensor will be designed, layed-out, and performance simulated, so that it can be manufactured and tested in Phase II.

* Information listed above is at the time of submission. *

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