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Reliable, High Temperature Silicon Carbide MOSFET

Award Information
Agency: Department of Defense
Branch: Army
Contract: W56HZV-07-C-0533
Agency Tracking Number: A052-236-3254
Amount: $729,999.00
Phase: Phase II
Program: SBIR
Solicitation Topic Code: A05-236
Solicitation Number: 2005.2
Timeline
Solicitation Year: 2005
Award Year: 2007
Award Start Date (Proposal Award Date): 2007-09-24
Award End Date (Contract End Date): 2009-09-24
Small Business Information
New Brunswick Technology Center 100 Jersey Ave. Building A
New Brunswick, NJ 08901
United States
DUNS: 042068101
HUBZone Owned: No
Woman Owned: No
Socially and Economically Disadvantaged: No
Principal Investigator
 X. Larry Li
 Sr. Research Engineer
 (732) 565-9500
 UnitedSiC@unitedsic.com
Business Contact
 Maurice Weiner
Title: Vice President
Phone: (732) 565-9500
Email: uscweiner@unitedsic.com
Research Institution
N/A
Abstract

This SBIR Phase II program, in response to topic number A05-236, aims at design and fabrication of a novel SiC power MOSFET to address the problems of (i) low channel mobility, (iii) low and unstable threshold voltage, and (iii) low gate oxide reliability under both high electric field and high temperature. Based on the successful Phase I feasibility demonstration of the concept, a physics-based device model will be optimized to guide the experimental efforts and to predict the device performance including DC and switching characteristics as well as temperature dependence. LMOSFETs and MOS capacitors will be used to optimize gate thermal oxide process conditions and to evaluate gate oxide quality and channel carrier mobility, targeting a field-effect channel mobility of 200cm2/Vs. Multiple batches of SiC power MOSFETs and lateral MOSFETs will be designed and fabricated, targeting systematically increased MOSFET power capability, consistently decreased device specific resistance, reproducible and stable threshold voltage, and reliable gate oxide for applications up to 200oC. Fabricated power MOSFET wafers will be diced and packaged for half-bridge inverter testing and successful devices will be delivered for independent evaluations. Phase III will be focused on addressing any remaining issues and on improving the device yield for commercial introduction of prototype SiC power MOSFETs.

* Information listed above is at the time of submission. *

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