AN ASSOCIATIVELY ADDRESSED SCALER ARRAY INTEGRATED CIRCUIT COMPONENT FOR A HIGH-RATE HISTOGRAMMING MEMORY

THE OBJECTIVE OF THE PROPOSED PROJECT IS THE DETAILED SPECIFICATION, DESIGN, AND DEVELOPMENT OF AN INTEGRATED CIRCUIT COMPONENT (CHIP) THAT WILL SERVE AS A NATURAL PART OF ONE TYPE OF HISTOGRAMMING MEMORY MODULE. THE HISTOGRAMMING MEMORY MODULE IN QUESTION IS THE TYPE THAT IS USED TO COLLECT ONE- OR TWO-DIMENSIONAL EVENT DATA GENERATED BY HIGH-RATE, ONE- OR TWO-DIMENSIONAL POSITION-SENSITIVE DETECTORS OF SCATTERED OR DIFFRACTED RADIATION UTILIZED AS A PROBE. THE DATA FROM SUCH EXPERIMENTS TYPICALLY IS DIVIDED INTO A LARGE NUMBER OF PICTURE ELEMENTS (PIXELS) AND HENCE HAS A LARGE RANGE (10(6) - 10(7) ELEMENTS) IN PIXEL ADDRESS SPACE. FURTHERMORE, FOR EXPERIMENTS CONDUCTED AT SOURCES OF HIGH INTENSITY PROBE RADIATION, SUCH AS SYNCHROTRON RADIATION SOURCES, DYNAMIC STUDIES BECOME FEASIBLE, WHERE THE DATA IS PARTITIONED AS A FUNCTION OF TIME AFTER SOME SAMPLE STIMULUS. THUS A HISTOGRAMMING MEMORY ADDRESS SPACE SUFFICIENT TO HOLD PIXEL DATA COVERING THE TOTAL PIXEL ADDRESS RANGE MUST BE AVAILABLE DURING EACH TIME SLICE (OR TIME FRAME). THE TOTAL AMOUNT OF HISTOGRAMMING MEMORY CAN BE INCREASED TO 10(9) OR 10(10) STORAGE LOCATIONS. THIS AMOUNT OF HIGH SPEED (20 NSEC UPDATE CYCLE)MEMORY WOULD BE PROHIBITIVELY EXPENSIVE FOR MOST CONTEMPLATED EXPERIMENTS. THE PRESENT PROPOSAL ASSUMES THATTHE DATA FOR SOME OF THESE EXPERIMENTS WOULD CONSIST OF "HOT SPOTS", ON A GENERAL BACKGROUND OF MUCH LOWER RATE AREAS, WHERE THE MAJORITY OF THE OCCUR IN A LIMITED REGION OF THE PIXEL SPACE. THE PROPOSED INTEGRATED CIRCUIT COMPONENT WOULD AUTOMATICALLY RECOGNIZE AND COUNT THE EVENTSIN THESE HOT SPOTS AT A HIGH RATE (50 MHZ) AND PASS THROUGH THE "BACKGROUND" LOW-RATE EVENTS TO A HISTOGRAMMING MEMORY CONTAINING MUCH LOWER SPEED (100 - 200 NSEC), RELATIVELY INEXPENSIVE MEMORY.