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THREE-DIMENSIONAL WAFER-SCALE INTERCONNECT AND PACKAGING USING PHOTOSENSITIVE GLASS-CERAMIC SUBSTRATES

Award Information
Agency: Department of Defense
Branch: Air Force
Contract: N/A
Agency Tracking Number: 6437
Amount: $229,500.00
Phase: Phase II
Program: SBIR
Solicitation Topic Code: N/A
Solicitation Number: N/A
Timeline
Solicitation Year: N/A
Award Year: 1989
Award Start Date (Proposal Award Date): N/A
Award End Date (Contract End Date): N/A
Small Business Information
Po Box 5937
Sherman Oaks, CA 91413
United States
DUNS: N/A
HUBZone Owned: No
Woman Owned: No
Socially and Economically Disadvantaged: No
Principal Investigator
 William J Jacobi
 (818) 981-8740
Business Contact
Phone: () -
Research Institution
N/A
Abstract

THE PURPOSE OF THIS PROJECT IS TO DEVELOP AND DEMONSTRATE AN INNOVATIVE NEW APPROACH TO MULTI-CHIP, WAFER-SCALE INTERCONNECT AND PACKAGING USING NEW PHOTOIMAGEABLE GLASS-CERAMIC AND POLYIMIDE MATERIALS THAT CAN BE PROCESSED WITH CONVENTIONAL PHOTOLITHOGRAPHY TECHNIQUES. THE SUPERIOR PROPERTIES OF THESE MATERIALS INCLUDE A CAPABILITY FOR PRECISION FABRICATION OF COMPLEX THREE-DIMENSIONAL STRUCTURES FOR PLANAR CHIP BONDING, DIRECT HEAT REMOVAL, WAFER STACKING FEEDTHROUGH VIAS AND MATCHED IMPEDANCE TRANSMISSION LINES. THE PHASE I EFFORT IS FOR A DEMONSTRATION OF THE NEW PACKAGING APPROACH BY FABRICATING AN IBM PC CLONE CPU/RAM ON A SINGLE ONE-INCH SQUARE SUBSTRATE WITH RECESSED CHIP CAVITIES. THE PHASE II EFFORT WILL INCLUDE DEMONSTRATIONS OF THERMAL AND WAFER STACKING VIAS AS WELL AS CONTROLLED IMPEDANCE LINES.

* Information listed above is at the time of submission. *

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