TESTING AND PACKAGING TECHNOLOGY FOR MULTI-GIGAHERTZ BANDWIDTH HIGH PINOUT DENSITY DIGITAL CIRCUITS

THIS PROPOSAL ADDRESSES THE NEED FOR DEVELOPING SUITABLE AND INNOVATIVE TECHNIQUES FOR TESTING AND PACKAGING OF MULTI-GIGAHERTZ BANDWIDTH ICS WITH HIGH PINOUT DENSITY. THE FIRST SECTION ADDRESSES THE CRITICALITY OF THE TESTING PROBLEM AND OBSERVES THAT THE TECHNOLOGY TO SOLVE THIS PROBLEM SATISFACTORILY IS CURRENTLY AVAILABLE, BUT NEEDS TO BE HARNESSED. THE NEXT SECTION ENUMERATES THE SPECIFIC TECHNICAL OBJECTIVES FOR THIS PROJECT. THE FOLLOWING SECTION COMPRISES FOUR SUBSECTIONS: (I) TESTER DESIGN GOALS (II) TWO PROMISING DESIGN APPROACHES, (III) FOUR CRITICAL AREAS THAT NEED ADVANCEMENTS IN THE STATE-OF-THE-ART, AND, (IV) A SPECIFIC LIST OF TASKS TO BE PERFORMED DURING PHASE I. THE NEXT AND FINAL TECHNICAL SECTION COVERS BRIEFLY RELATED WORK IN THIS FIELD. WHILE MOST OF THE PROPOSAL DEALS WITH TESTING TECHNIQUES, A NOVEL IDEA FOR ULTRAHIGH DENSITY PACKAGING AND 'IMPEDANCE TRANSPARENT DESIGN' IS PRESENTED. A NOVEL DESIGN APPROACH FOR A TESTER FRONT END CAPABLE OF GENERATING 256KBITS LENGTH TEST VECTORS AND STORING AN EQUALLY LONG RESULT IS GIVEN, AND A FEASIBILE TECHNIQUE FOR IMPLEMENTING A MODULAR TESTER ARCHITECTURE IS PRESENTED.