You are here

APPLICATION OF VLSI TO VECTOR ACCUMULATORS AND INTEGRATING TIME TO DIGITAL CONVERTER

Award Information
Agency: Department of Defense
Branch: Defense Advanced Research Projects Agency
Contract: N/A
Agency Tracking Number: 6004
Amount: $49,968.00
Phase: Phase I
Program: SBIR
Solicitation Topic Code: N/A
Solicitation Number: N/A
Timeline
Solicitation Year: N/A
Award Year: 1987
Award Start Date (Proposal Award Date): N/A
Award End Date (Contract End Date): N/A
Small Business Information
2215 Addison
Houston, TX 77030
United States
DUNS: N/A
HUBZone Owned: No
Woman Owned: No
Socially and Economically Disadvantaged: No
Principal Investigator
 DR FHOWARD K SCHMIDT
 (713) 529-9040
Business Contact
Phone: () -
Research Institution
N/A
Abstract

DESIGN, SIMULATION, FABRICATION, AND EVALUATION OF A PROTOTYPE VERY LARGE SCALE INTEGRATION (VLSI) DATA ACQUISITION SUBSYSTEM IS PROPOSED. AVAILABLE STATE-OF-THE-ART ONE MICRON CMOS TECHNOLOGY MAY ALLOW INCORPORATION OF MORE THAN 128 CHANNELS OF 24-BIT 300 MHZ COUNTERS INTO A SINGLE INTEGRATED CIRCUIT. A PROTOTYPE SYSTEM OF SIMPLE REPEATED CELLS OF COUNTERS, CONTROL AND I/O BUFFERS HAS BEEN DESIGNED FOR THE EVALUATION OF THE FEASIBILITY OF CONSTRUCTING INTEGRATED NUCLEAR DATA SUBSYSTEMS AND PRE-PROCESSORS. THE PROTOTYPE DEVICE HAS VERSATILE CONTROL CIRCUITRY ALLOWING OPERATION AS A MULTICHANNEL SCALER (MCS), A ZERO DEAD-TIME INTEGRATING TIME-TO-DIGITAL CONVERTER (ITDC), OR A VECTOR ACCUMULATOR (VA). CONSTRUCTION OF SPECIFIC DATA ACQUISITION SYSTEMS IS INTENDED IN FOLLOW ON WORK AND IS DISCUSSED.

* Information listed above is at the time of submission. *

US Flag An Official Website of the United States Government