Advanced Architectures for Interference-Tolerant Digital Receiver

The goal of this project is to (1) develop high dynamic range direct RF analog-to-digital converters (ADCs), providing enhanced immunity to high in-band intereference, and (2) use multiple synchronous converters to enable direct digital reception from a multi-antenna array. HYPRES has been developing a superconducting digital-RF receiver system for the Navy and other DoD users, based on an ultrafast ADC (sampled at 20 GHz or more), featuring outstanding linearity due to intrinsic quantum accuracy. This ADC design has matured over the last decade and already exhibits an impressive spur-free-dynamic range (SFDR) greater than 100 dB. Further substantial increase in performance requires a major innovative next generation design. We propose a more complex multi-rate quantizer design that allows the ADC dynamic range to be increased by at least 2 bits, for a total of 3.5 bits in conjunction with ongoing process improvements. We also propose to implement an advanced receiver architecture using multiple ADCs synchronized to a common clock to accommodate multiple inputs from one or more antenna arrays. Initial designs of multi-rate ADC and the multi-input receiver architecture will be completed in Phase I. Incorporation of these improvements into a complete digital-RF receiver will be completed in Phase II.BENEFITS: A broadband receiver with high linearity and dynamic range will be significantly more tolerant of cosite interference that has long been a major concern in Navy SIGINT and communication systems. Furthermore, synchronous detection from multiple antennas has broad applications to digital beamforming and direction finding. Receivers that incorporate similar components may also be applicable to commercial wireless communications, SATCOM, and radar systems.