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Object-Accelerated Computational Fabric

Award Information
Agency: Department of Defense
Branch: Defense Advanced Research Projects Agency
Contract: W31P4Q-08-C-0141
Agency Tracking Number: 07SB2-0117
Amount: $99,000.00
Phase: Phase I
Program: SBIR
Solicitation Topic Code: SB072-008
Solicitation Number: 2007.2
Timeline
Solicitation Year: 2007
Award Year: 2007
Award Start Date (Proposal Award Date): 2007-12-13
Award End Date (Contract End Date): 2008-08-15
Small Business Information
3680 Boulder Hwy.
Las Vegas, NV 89121
United States
DUNS: 129971573
HUBZone Owned: No
Woman Owned: No
Socially and Economically Disadvantaged: No
Principal Investigator
 Craig Steele
 President
 (702) 845-4582
 steele@exogi.com
Business Contact
 Craig Steele
Title: President
Phone: (702) 845-4582
Email: steele@exogi.com
Research Institution
N/A
Abstract

CPU technology has progressed to a point of diminishing marginal returns in its current direction. The great success of the highly pipelined sequential processor has now become a hindrance to the efficient scalability for the evolutionary escape route of cookie-cutter chip multi-processor (CMP) designs. RISC instruction sets exist because they are easy to decode and pipeline, but they have relatively low information density and operate on similarly primitive data types. If we look at the codes these CPUs are running, they are largely object-oriented languages. The lesson learned in the software world is that programmer productivity is relatively constant number of lines of code per day, whether assembly language or a much higher-level of abstraction in a modern object-based language. The information density and expressivity of the object-oriented language is much greater, as is the computational effort induced by each object method invocation. This is a good thing and should be emulated by hardware designers. We propose a package of novel several hardware-assisted object-based techniques to increase the value of our limited processor-to-network interfaces and the generally useful scalability of future CMP designs.

* Information listed above is at the time of submission. *

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