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HIGH PERFORMANCE CMOS DIGITAL INTEGRATED CIRCUITS USING SI1-XGEX PMOSFETS

Award Information
Agency: Department of Defense
Branch: Defense Advanced Research Projects Agency
Contract: N/A
Agency Tracking Number: 18316
Amount: $49,990.00
Phase: Phase I
Program: SBIR
Solicitation Topic Code: N/A
Solicitation Number: N/A
Timeline
Solicitation Year: N/A
Award Year: 1992
Award Start Date (Proposal Award Date): N/A
Award End Date (Contract End Date): N/A
Small Business Information
3152 Kashiwa Street
Torrance, CA 90505
United States
DUNS: N/A
HUBZone Owned: No
Woman Owned: No
Socially and Economically Disadvantaged: No
Principal Investigator
 V. Raman
 (310) 534-3666
Business Contact
Phone: () -
Research Institution
N/A
Abstract

WE PROPOSE TO DEVELOP ULTRA FAST LSI/VLSI CMOS CIRCUITS USING SI1-XGEX CHANNEL PMOS AND SI CHANNEL NMOS DEVICES INTEGRATED ON THE SAME CHIP SUITABLE FOR STRATEGIC DEFENSE SYSTEMS. SINCE THE MOBILITY OF THE PMOS SIGE CHANNEL DEVICES ATLEAST BY 50% THE CMOS CIRCUITS WILL HAVE HIGHER PACKING DENSITY (DUE TO SMALLER PMOS CELLS) AND HIGHER SPEED. WE WILL IDENTIFY A SUITABLE PROCESS COMPATIBLE WITH EXISTING CMOS TECHNOLOGY WITH MINIMAL MODIFICATIONS. THE GATE DIELECTRIC (SILICON DIOXIDE) LAYER WILL BE THERMALLY GROWN USING A SILICON CAP LAYER GROWN ON THIS SIGE ACTING AS THE CHANNEL LAYER FOR THE PMOS DEVICES. THE CHANNEL SIGE LAYER WILL BE UNDOPED AND THE VALENCE BAND DISCONTINUITY WILL RESULT IN A MODULATION DOPING CONTRIBUTING TO FREE HOLES CONFINED IN THE CHANNEL. WE WILL OPTIMIZE THE CHANNEL LAYER, CAP LAYER AND BUFFER LAYER THICKNESSES ALONG WITH THE DOPING CONCENTRATIONS FOR ACCEPTABLE PMOS THRESHOLD VOLTAGE. IN PHASE I, WE WILL DELINEATE THE FABRICATION PROCESS AND DESIGN THE DEVICE STRUCTURE. WE WILL ALSO DESIGN SEVERAL BASIC CELLS SUING THIS EXCITING MIXED CMOS TECHNOLOGY FOR VARIETY OF DIGITAL AND SIGNAL PROCESSING CIRCUITS AND OPTIMIZE THE DESIGN USING PROCESS, DEVICE AND CIRCUIT SIMULATIONS. ANTICIPATED BENEFITS: HIGH SPEED DATA PROCESSORS, HIGH DENSITY CMOS DIGITAL CIRCUITS AND FAST VLSI SYSTEMS.

* Information listed above is at the time of submission. *

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