Modular, Rapid, Common Hardware-in-the-loop Framework Development

The objective of this proposal is to demonstrate the feasibility of producing a multi-node communication network with low latency for use in the hardware-in-the-loop (HWIL) test environment. In the HWIL environment, multi-node connectivity latencies ideally would be at or near zero to prevent the masking of properties of equipment and protocols being tested. While ideal from a theoretical point of view, multi-node zero latency connectivity is not practical. As the performance of equipment and protocols being tested improves, the latency of connectivity begins to mask and, in some cases, even distort test results to the extent that meaningful scientific conclusions regarding the items being tested are difficult to achieve. WideBand Low Latency Networking (WLLN) is applicable to HWIL test environments. Port to port latency of less than 20 nanoseconds is achievable resulting in an order of magnitude improvement over state-of-the-art InfiniBand products. The Phase I technical objective of this project is research and develop a low latency, multi-node communication architecture based on the concept of WideBand Low Latency Networking technology.