Computationally Assisted Electronic Hardening

Reliable and sensitive aerial defense applications (missile seekers, avionics, remote sensing) demand that electronic components be resistant to ionizing radiation from nuclear weapons and upper atmosphere/terrestrial sources. CFDRC, in collaboration withHoneywell and Vanderbilt University, is proposing to develop electronic-hardening concepts at the process, device and primitive cell level to achieve significant radiation tolerance. The innovative rad-hard circuit design technology will include: 1) Anintegrated computational environment to provide quantitative assistance in developing and refining rad-hard processes (SOI) and designs (shallow trenches, guard rings). This step would utilize 3D device simulations with advanced semiconductor modelsenhanced with radiation effects; 2) Numerical, automated optimization of primitive logic and memory cell process parameters and designs for mitigation of Single Event Effects (SEE) and Total Ionizing Dose (TID) in submicron CMOS technologies. 3)Calculation of key operational parameters of the designed cells, to indicate that the designs will tolerate radiation exposure to specified levels. Special attention will be given to single event upset (SEU) vulnerability. In Phase II, theelectronic-hardening software will be enhanced with total ionizing dose analysis capability, and optimized designs of primitive logic and memory cells will be fabricated and electrically characterized to demonstrate hardness to SEE and TID. All federaland commercial organizations that are involved in launching vehicles into space (remote sensing, surveillance, weather) would benefit greatly by having access to high-performance, radiation-hardened microelectronics that are readily and cost-effectivelyproduced. DoD also has many ground-based applications for radiation-hardened microelectronics.