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Strain-Enhanced Tunnel Diode Technology

Award Information
Agency: Department of Defense
Branch: Missile Defense Agency
Contract: DASG60-02-P-0108
Agency Tracking Number: 02-0236
Amount: $69,645.00
Phase: Phase I
Program: SBIR
Solicitation Topic Code: N/A
Solicitation Number: N/A
Timeline
Solicitation Year: N/A
Award Year: 2002
Award Start Date (Proposal Award Date): N/A
Award End Date (Contract End Date): N/A
Small Business Information
386 Spanish Wells Road, Building B, Suite 3
Hilton Head Island, SC 29926
United States
DUNS: 072016632
HUBZone Owned: No
Woman Owned: No
Socially and Economically Disadvantaged: No
Principal Investigator
 Rona Belford
 President
 (843) 681-7688
 belford@hargray.com
Business Contact
 Rona Belford
Title: President
Phone: (843) 681-7688
Email: belford@hargray.com
Research Institution
N/A
Abstract

"We intend to increase by an order of magnitude, the current density of silicon-based tunnel diodes. This increase directly relates to a corresponding increase in performance (speed). Apart from being the fastest of all microelectronic devices, tunneldiodes (TDs) have negative differential resistance, which gives them unusual circuit qualities. When attached to integrated circuits they improve the circuit parameters (by two or three times). They enable fewer transistors to be used, power consumption islowered, circuit speed is increased, and the layout area is reduced. TDs are being developed for use in high-speed radar & communications, signal processing, data conversion and memory. The integration of tunnel diodes into silicon ICs is therefore highlydesirable. Si tunnel diodes have a current density of up to ~10 kA/cm2, we can double this figure by low-level straining (0.05%). We believe further optimization up to 1% strain would yield figures for Si-based TDs comparable to III-V TD devices (100kA/cm2). Integration of high current density (100kA/cm2), low capacitance, tunnel diodes incorporated into ICs has great benefits in e.g. lowering power consumption by a factor of 2, while increasing overall circuit speed by a factor of 2 and reducinglayout area by a factor of 3."

* Information listed above is at the time of submission. *

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