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DoD 2013.2 SBIR Solicitation

DoD 2013.2 SBIR Solicitation

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Agency: Department of Defense
Branch: Defense Microelectronics Activity
Program/Year: SBIR / 2013
Solicitation Number: 2013.2
Release Date: April 24, 2013
Open Date: May 24, 2013
Close Date: June 26, 2013
DMEA132-001: Miniaturized RF over Fiber
Description: OBJECTIVE: Design and prototype a capability to use fiber optic cable to simultaneously distribute power (i.e power over fiber) while providing full duplex information flow. The capability will allow miniature microwave system components to be distributed over a relatively long distance (i.e. 30 meters or more) via fiber optics. For example, a processing node (within a microwave system) provides power over fiber optics to a remote RF node that has a Global Positioning System (GPS) and/or SATCOM capability. The capability would allow for the RF node GPS to send position information back to the processing node via the fiber optic cable. DESCRIPTION: Replacing coaxial cables with fiber optic cables for long distance remote installation of antennas from transmitters is desirable to minimize line losses, improve antenna matching and efficiency, reduce weight, reduce or eliminate electromagnetic interference (EMI), improve strength and flexibility, and allow easier deployment. Current RF over fiber optics systems are typically designed to support hardwired capability into ships, fixed buildings and laboratories. These systems utilize relatively large electronics components for transceivers and are not optimized for small portable systems. Critical war fighter capabilities utilizing microwave RF systems like GPS, satellite telephony, and satellite communications are limited to open sky areas. War fighters deployed in buildings, hardened shelters, and armored vehicles cannot easily deploy antennas (and potentially communication modules) to remote locations. Fiber optics is ideal for distributed systems due to their light weight, low transmission loss, and flexibility. Highly innovative electronics solutions are needed to allow war fighters to create distributed microwave systems using fiber optics. These devices must be small enough for tactical applications allowing dismounted war fighters to rapidly distribute GPS and RF communications into buildings, hardened facilities, or vehicles. An ideal solution would have all power to the transmission/antenna section conducted over the fiber (power-over-fiber). The antenna section should be tunable to allow the war fighter to connect RF devices of different frequencies (GPS, SATCOM, etc.). The design must be power frugal for maximum battery life and allow simultaneous connection to multiple RF devices, sharing a common antenna. A mixed cable solution will not be considered creative or innovative design. PHASE I: Conduct research on state of the art solutions for miniaturizing fiber optic transceivers and providing power-over-fiber. Design and develop an innovative approach to distribute microwave RF devices using fiber optic cables. Propose a solution and determine the technical capabilities of the proposed design. PHASE II: Build a prototype system based upon the Phase I design. Identify radios of two separate frequencies for the prototype (e.g., GPS, SATCOM, GSM). Demonstrate the prototype system in an environment with realistic test conditions. PHASE III: There may be opportunities for further development of these devices for use in a specific military or commercial application. During a Phase III program, the contractor may refine the performance of the design and produce pre-production quantities for evaluation by the Government. POTENTIAL DUAL USE APPLICATIONS: The proposed system will be applicable to both commercial and military RF devices. Potential civilian applications include: GPS time adjusted clocks, cell phone and satellite phone transceivers for home use, laboratory remoting, and portable communications. REFERENCES: 1. Basanskaya, Anna,"Electricity Over Glass,"IEEE Spectrum, Oct 2005. 2. Castello, Richard, J. Fajardo, M. Ryan, and M. Ferguson,"Technical Requirements Document (TRD) for NAVSI Fiber Optic Antenna Link (FOAL),"Technical Document 3256, Jan. 2012. 3. Crane, Scott, and C. Ekstrom, P. Koppang, and W. Walls,"High-Performance RF Optical Links,"41th Annual Precise Time and Time Interval (PTTI) Meeting, Nov 2009. 4. Dickerson, Mike,"Increased Submarine RF Capacity for Sensors and Survellance (RFOF/iPON), Phase-II Final Report, 31 Aug 2012. 5. Dickerson, Mike,"RF Over Optical Fiber, Phase-II Final Report, Sep. 2011. 6. Kanter, Gregory S., and P Kumar,"Advanced Radio Frequency and Optical Connectivity To Support Network-Centric Operations, Final Report", FA8650-06-M-4408, Jan. 2007.
DMEA132-002: High Resolution Three-Dimensional Digital Reconstruction of Integrated Circuits
Description: OBJECTIVE: Develop a system for the accurate identification and analysis of semiconductor materials with integrated, high-resolution imaging capability for the three-dimensional digital reconstruction of integrated circuits (ICs). DESCRIPTION: As semiconductor geometries continue to diminish, so too does the applicability of traditional sample preparation tools. As the thickness of metal layers in modern ICs drops below 100nm, existing mechanical tools become severely limited by their lack of resolution; mechanical tools are physically limited to middle sub-micron Z-axis resolution (i.e., greater than 100nm) over an entire IC area; thus, planar material removal results are unreliable at smaller technology nodes. Available non-mechanical tools (e.g., FIB), on the other hand, are prohibitively slow due to extremely gradual material removal. Ultrafast laser ablation systems have been demonstrated to have Z-axis resolution in the 100nm range, but final surface roughness can prohibit detailed analysis of the underlying circuitry. Therefore, a deep sub-micron resolution processing system with a high throughput is required for timely, accurate and precise post-silicon analysis of modern ICs. Additionally, handling and transfer of samples (between processing and imaging apparatuses) significantly contributes to the damage and contamination of delicate ICs. For this reason, in situ imaging capability is necessary to reduce these hazards and to increase the overall throughput of the system. Finally, the ability to operate in three dimensions is important because, as device architecture enters the three-dimensional frontier, the reconstruction of the de-processed IC must also become three-dimensional to properly represent the functionality of the three-dimensional architecture. PHASE I: Identify concepts and methods for failure analysis and reverse engineering using tools and techniques for the identification of semiconductor materials (e.g., Cu, Al, Si, SixOx, SixNx, W, Ti, GaAs) for the purpose of representing, in three dimensions, the constituent circuits and interconnections. Investigate existing techniques for the three-dimensional delineation of semiconductor materials within ICs. Perform a study to facilitate the design of an innovative processing/imaging system. The goal of the innovation is to process, image and digitally reconstruct (in three dimensions) the constituent features of a modern IC (e.g., interconnect traces, transistor gates, diffusion regions, vias, contacts) while adhering to the following constraints: - Z-Axis Resolution: & #8804;40nm - Image Magnification: & #8805;20,000x - Image Resolution: & #8805;50k (independent) pixels per m2 - Throughput: & #8805;0.025mm3 reconstructed per day (8 hour operator time, 24 hour tool time) @ 50nm Z resolution - Surface Roughness: & #8804;5nm RMS Deliver a report of research and innovation that presents tradeoffs between the new approach and existing technology. If any of the above constraints cannot be adhered to, the report must include relevant research and rationale. Offerors may provide alternative parameters that are both attainable and consistent with the goals summarized above. The report must also include all generated files (e.g., CAD drawings) and a program plan for system development. PHASE II: Based on the aforementioned study and applicable development/innovation, devise a novel approach and design the processing/imaging system. Determine all design decisions, understanding that implementation of the system should be in a laboratory environment with typical facility resources (e.g., nitrogen gas, DI water, 110V or 240V power @ 60Hz) and spatial restrictions. Develop a prototype of the Phase I design and demonstrate its operation. Re-verify the performance over multiple dissimilar, modern ICs (i.e., 90nm technology node or better) and develop a test plan to fully characterize the prototype. Test the prototype and deliver the prototype, characterization results, all generated files (e.g., CAD drawings, test results), operation instructions, and the test plan to the Government for further testing and verification. PHASE III: There may be opportunities for further development of this system for use in a specific military or commercial application. During a Phase III program, offerors may refine the performance of the design and produce pre-production quantities for evaluation by the Government. POTENTIAL DUAL USE APPLICATIONS: The High Resolution Three-Dimensional Digital Reconstruction system would be applicable to both commercial and government semiconductor device research and failure analysis. Government applications include failure analysis and characterization of advanced semiconductor fabrication processes. Commercial functions include three-dimensional material analysis for industrial, biological, and semiconductor applications. REFERENCES: 1. D. Karnakis,"Ultrafast Laser Nanomachining: Doing More With Less,"Commercial MicroManufacturing, November 2008. 2. D. Wei, S. Jacobs, S. Modla, S. Zhang, C. Young, R. Cirino, J. Caplan, and K. Czymmek,"High-resolution three-dimensional reconstruction of a whole yeast cell using focused-ion beam scanning electron microscopy,"BioTechniques 53:41-48, July 2012. 3. M. Bohr, K. Mistry,"Intel"s Revolutionary 22 nm Transistor Technology,"Intel Press Release (http://newsroom.intel.com/docs/DOC-2032#overview), May 2011. 4. International Technology Roadmap for Semiconductors, 2007 Edition, Interconnects. 5. T. Hazeldine, K. Duong,"Microsurgery for Microchips,"Materials World 10-12, November 2003 6. Information on the Defense Microelectronics Activity may be found at: http://www.dmea.osd.mil/